As a technique examined by the present inventors, for example, the following technique is conceivable in a semiconductor device including a phase change memory. A storage element uses a Ge—Sb—Te based or Ag—In—Sb—Te based chalcogenide material (or phase change material) containing at least antimony (Sb) and tellurium (Te) as a material of a storage layer. Further, a diode is used as a selection element. The array configuration of a phase change memory using a chalcogenide material and a diode is described in, for example, “IEEE International Solid-State Circuits Conference, Digest of Technical Papers”, USA, 2007, pp. 472-473 (Non-Patent Document 1).
FIG. 2 is a view extracting a local memory-cell array LCA from the memory core configuration described in FIG. 26.1.2 of the Non-Patent Document 1. Memory cells MC00 to MCnn in which a resistive storage device R using a phase change material and a diode for select D are connected in series are disposed at intersections of (n+1) local bit-lines LBL0 to LBLn and (n+1) word lines WL0 to WLn. Each of the local hit-lines LBL0 to LBLn is connected to a global bit-line GBL0 through NMOS transistors MNYS0 to MNYSn. The transistors MNYS0 to MNYSn are controlled by local column select signals LY0 to LYn connected to the respective gate electrodes thereof. More specifically, when any one of the transistors NMYS0 to MNYSn is activated and made conductive, any one of the local bit-lines LBL0 to LBLn is electrically connected to the global bit-line GBL0. Note that NMOS transistors MND0 to MNDn are inserted between the local bit-lines LBL0 to LBLn and ground terminals VSS, respectively. The transistors MND0 to MNDn are controlled by a local bit-line discharge signal LBLDIS connected to respective gate electrodes thereof.
“IEEE International Electron Device Meeting, Digest of Technical Papers”, USA, 2007, pp.307-310 (Non-Patent Document 2) describes temperature conditions capable of retaining the stored information for ten years. According to the Non-Patent Document 2, by adding indium (In) to a chalcogenide material, the operable temperature range from 85° C. to 105° C. is expanded up to 150° C. Since the operable temperature range is expanded, the application range of the phase change memory is expanded.